|
|
GET
QUOTE |
|
|
PRINT
DATA SHEET |
|
|
VIEW CART |
|
|
PREVIOUS PAGE |
|
|
Fastcom®: SuperFSCC-104-LVDS
|
PC/104+ Bus Dual Port LVDS/RS644 Synchronous Communications Adapter w/DMA
|
| Adapter Only
$725.00
|
| |
| Adapter & Cable
$764.00
|
|
|
|
Fastcom®:
SuperFSCC-104-LVDS
Cable |
| |
2x25 Header Connector to two DB25 plugs
(Optional) |
| Cable Only
$39.00
|
|
Designed to comply with the latest
PC/104+ specifications (Version 2.2), the Fastcom: SuperFSCC-104-LVDS Universal PC/104+ Bus adapter will operate in both 5V and 3.3V PCI
slots. This means the card will work in the high speed
PCI-X slots commonly found in most new servers, as well
as the standard PCI slots in desktop PC's. This flexibility
allows for a single serial interface board to be used across
a wide range of different types of computers including
both current and future computing systems.
The Fastcom: SuperFSCC-104-LVDS adapter is the one of the most
advanced synchronous communications adapters in the industry, supporting data rates up to 50 Mbits/s¹.
The Fastcom: SuperFSCC-104-LVDS is a dual channel adapter, with each
one being individually configurable to use HDLC/SDLC, ASYNC
(using 16C950 UARTS), or X-SYNC protocols. Although similar
to the ESCC and SuperFastcom families of adapters, the
SuperFSCC-104-LVDS expands on our previous adapters.
The most notable expansion is the longevity of the
components of the board. Faced with the inevitability of
obsolescence, Commtech decided to put an end to the lifespan
problems that plague most computing customers. We designed
a serial communications controller with our customers’ needs
in mind, and built a card around it. Wholly designed and
owned by Commtech, Inc, this FPGA based SCC has most of
the features that you are used to seeing in a quality Fastcom
product. It also includes a few new features that come
directly from customer requests. If the existing FPGA technology
is ever discontinued by the chip manufacturer,
the design can simply be re-targeted to the next generation
of FPGA chip with no impact on compatibility.
- Software drivers and example programs are included
for Windows 2000, XP, 2003, 2003x64, VISTA, VISTAx64, Windows 7, Windows 7x64, and Linux kernels
2.4 and 2.6
|
| LINKS: |
Fastcom: SuperFSCC-104-LVDS Product Manual |
| SPECIFICATIONS: |
- COMM. CONTROLLER: Fastcom F-Core
- INTERFACE: ANSI/TIA/EIA-644 LVDS
- CONNECTOR CONFIGURATION:
- DB62 to two DB25 cable assembly
- BUS INTERFACE: PC/104+ Compliant Version 2.2
- BAUD RANGE: Using the user independent
programmable clock generator in conjunction with the baud
rate register, virtually any baud rate from DC to 50 MBits/s¹ can
be attained.
|
| POWER REQUIREMENTS: |
|
| ENVIRONMENT: |
- Operating Temperature Range: -40 to +85 C
- Humidity: 0 to 90% (non-condensing)
|
| FEATURES: |
- Never Obsolete
- High speed: Up to 50Mbits/s¹
- Drivers: LVDS / RS-644
- True-Async mode. Each port can be set to use the on-board
16C950 UARTs and can be used as a standard serial (COM)
port.
- Automatic RS-485 handling
- Transmit and Receive status LED’s for each port.
- On board 100 Ohm terminator for each receive
differential pair
- Two independent full duplex serial channels
- Data clocking mechanism independently selectable
per channel per direction
- Externally generated Rx and Tx clocks
- Internally generated Rx and Tx clocks
- On chip DPLL clock recovery
- Independent baud rate generators
- FIFOs
- RxFIFO = 8KB per port (non-uart modes)
- TxFIFO = 4KB per port (non-uart modes)
- Programmable interrupt trigger levels (watermark)
- Data protocols
- HDLC/SDLC
- Arbitrary maskable sync sequence of up to 4 bytes
in length (X-Sync)
- Transparent data without character framing
- Data encoding schemes:
- NRZ, NRZI, FM0/FM1, Manchester, Differential Manchester
- Selectable frame sync signals
- Pulse width of one clock at first bit of data
- Pulse width of one clock at last bit of data
- Pulse width of the entire frame
- Optionally insert a variable number of clock cycles
between data and FSS
- Selectable polarity
- Optional data flow control using modem control lines
(RTS, CTS)
- Programmable 8-bit preamble and postamble with selectable
repetition rate (1 to 255 repetitions)
- Data can be oriented as selectable MSB first or LSB first
- Interframe time fill: idle as repetitive 1’s, flags,
or sync sequences
- CRC Support
- Automatic handling in the transmit/receive direction
- CRC-CCITT (also known as CRC16-ITU) (HDLC), CRC32
(HDLC), CRC16, CRC8 (HDLC)
- Transparent CRC option
- Reset as 0’s / 1’s
- Continuous transmission of 1 to 4096 bytes
- Selectable data rates
- Synchronous (internally clocked) data rates up
to
50 Mbits/s
- Synchronous (externally clocked) data rates up
to
30 Mbits/s
- Asynchronous (DPLL clock recovery) data rates up
to
12.5 Mbits/s
- These maximum data rates are estimates. They are
greatly affected by a number of different factors.
See the data rates section of the manual for more
details.
- Data and clock inversion
- Interruptible hardware timer
- Transmit a single frame on the expiration of the hardware
timer
- Transmit a single frame on the detection of external signal
DATA PROTOCOLS:
- HDLC/SDLC
- Automatic flag detection and transmission
- General frame format: 0x7e,info,CRC,CRC,[CRC,CRC,]0x7e
- Frame format with maskable address enabled: 0x7e,address,[address,]info,CRC,CRC,[CRC,CRC,]0x7e
- Zero insertion/deletion
- One insertion/deletion
- Shared flag mode: opening flag and closing flag
of back-to-back frames can use the same flag.
- Error detection (abort, overrun, underrun, CRC
error, too long/short frame)
- Can use CRC8, CRC-CCITT, or CRC32
- Arbitrary Sync Sequence (X-Sync)
- Any begin/end frame sync sequence of up to 4
bytes
- Frame format: SYN1,[SYN2,SYN3,SYN4,]info,[CRC,CRC,
CRC,CRC,][TCR1,TCR2,TCR3,TCR4]
- Maskable: can select all or parts of the sync
sequence to be a sync match
- Termination sequence detection up to 4 bytes
(maskable)
- Shared flag mode: opening flag and closing flag
of back-to-back frames can use the same flag.
- Error detection
- Can use any of the available CRC methods
- Transparent Mode
- Fully bit transparent (no framing or bit manipulation)
- Can synchronize using selectable frame sync signals
- Documentation, and software drivers included, cable is optional
- Designed and manufactured by COMMTECH, INC. Wichita,
Kansas, USA
For a more complete and detailed list of features available
on this card, please see the complete SuperFSCC-104 manual. |
|
|
¹Maximum
data rates are estimates. They are greatly affected by a
number of different factors. See the data rates section of
the manual for
more details. This is possible as long as the operating parameters are within reason. For instance, you cannot expect to perform continuous, full duplex operation at 50Mbps with 2 byte frames. This will require reasonable sized frames with a minimum size of around 1024 bytes. If you have any question about whether the card can meet your needs, please contact Technical Support. |
|
|
|